For quality assurance when fabricating integrated semiconductor circuits and also packaged or mounted integrated circuits, one test step is the determination of working, as yet unseparated, chips on a semiconductor wafer. Another test is performed on the semiconductor chips packaged in a package as a finished item. The test costs for the integrated semiconductor circuits or chips and also for the finally mounted packaged integrated circuits make up a significant proportion of the total costs in semiconductor fabrication.
In this context, the continually rising integration density of integrated semiconductor circuits causes a series of problems in the implementation of an inexpensive, fast and reliable production test. A problem with observability exists as the number of internal components of an integrated semiconductor circuit rises much more quickly than the number of connection pins which are present on a package. In addition, the typical system frequencies are on the rise, which means that a test under operating conditions requires ever more expensive high performance testers. Additionally, the clock frequency often does not increase to the same degree as, by way of example, a number of memory cells in a memory integrated in the system. This lead, for the same test algorithms, to an increasing test time and hence rising test costs per product. Likewise, the consistent transmission of the test results in currently different standards presents a logistical challenge, particularly when using different subcontractors for separate wafer production and mounting, for example.
A reduction in test time and in test and also logistical costs can thus be achieved most effectively by virtue of a combined approach covering circuit design, test concept, tester and mounting design and logistics. Such an improved test method is known, by way of example, from EP 1 178 323, in which integrated circuits to be tested each have integrated self-test units (built-in self-test units or “BISTs”) and a self-test is performed at an earlier time than the reading of the test results for the self-test.
FIG. 1 shows a simplified plan view of a semiconductor wafer W having a multiplicity of integrated semiconductor circuits IC formed thereon, in line with these conventional methods. In this case, all the integrated circuits IC on a semiconductor wafer W are actually supplied with a voltage supply at wafer level, which means that the self-test units produced in the multiplicity of integrated circuits IC can actually perform a contemporaneous self-test. Thus, only the test information obtained or the test result needs to be read by making individual contact, for example, and faulty integrated circuits IC are subsequently marked in the usual manner using these test results in the event of an operating fault.
A normal marking method in this context is “inking”, where functionally impaired integrated circuits are provided with an ink dot which subsequently, as a selection criterion for downstream mounting units, results in accordingly marked chips being rejected.
A drawback in this context, however, is that particularly when BISTs are used, the test results need to be stored in a memory. On the one hand, this can be done in volatile electrically readable memories or in nonvolatile electrically readable memories, with the volatile memories requiring a constant power supply. On the other hand, nonvolatile memories result in increased production costs and require additional voltages which are increased as compared with a standard supply voltage.
For this reason, the exclusive use of BIST methods or self-test methods particularly for the wafer test has still not been implemented at a broad level, despite the potentially high cost advantage, since after the self-test every integrated semiconductor circuit or every chip IC needs to be brought into contact with a tester again and the result subsequently needs to be evaluated. Since these handling and contact times take up a large portion of the test time and hence of the test costs, however, the advantages of these self-test methods (BIST methods) are significantly reduced.